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| ? 2008 microchip technology inc. ds22029d-page 1 34aa02/34lc02 features: ? permanent and resettable software write-protect for lower half of the array (00h-7fh) ? single supply with operation down to 1.7v ? low-power cmos technology: - read current 1 ma, typical - standby current, 100 na, typical ? 2-wire serial interface bus, i 2 c? compatible ? cascadable up to eight devices ? schmitt trigger inputs for noise suppression ? output slope control to eliminate ground bounce ? 100 khz and 400 khz compatibility ? 1 mhz clock for lc versions ? page write time 3 ms, typical ? self-timed erase/write cycle ? 16-byte page write buffer ? esd protection > 4,000v ? software write protection for lower 128 bytes ? hardware write protection for entire array ? more than 1 million erase/write cycles ? data retention > 200 years ? 8-lead pdip, soic, t ssop, msop and tdfn packages ? 6-lead sot-23 package ? pb-free and rohs compliant ? available for extended temperature ranges: - industrial (i): -40c to +85c - automotive (e): -40c to +125c device selection table package types description: the microchip technology inc. 34aa02/34lc02 (34xx02*) is a 2 kbit electrically erasable prom capable of operation across a broad voltage range (1.7v to 5.5v). this device has two software write- protect features fo r the lower half of the array, as well as an external pin that can be used to write-protect the entire array. this allows the system designer to protect none, half, or all of the array, depending on the application. the device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. low- voltage design permits operation down to 1.7v, with standby and active currents of only 100 na and 1 ma, respectively. the 34xx02 also has a page write capability for up to 16 bytes of data. the 34xx02 is available in the standard 8-pin pdip, surface mount soic, tssop, msop and tdfn packages. the 34xx02 is also available in the 6-lead, sot-23 package. part number v cc range max. clock frequency temp ranges 34aa02 1.7-5.5 400 khz (1) i,e 34lc02 2.2-5.5 1 mhz i,e note 1: 100 khz for v cc <1.8v a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda pdip/soic/tssop/msop/tdfn a0 a1 a2 v ss wp scl sda v cc 8 7 6 5 1 2 3 4 sot-23 6 2 4 sda v cc v ss a0 a1 5 3 1 scl 2k i 2 c ? serial eeprom software write-protect *34xx02 is used in this document as a generic part number for the 34aa02/34lc02 devices.
34aa02/34lc02 ds22029d-page 2 ? 2008 microchip technology inc. block diagram i/o control logic memory control logic xdec hv generator standard array software write- write-protect circuitry ydec v cc v ss sense amp. r/w control sda scl a0 a1 a2 wp protected area (00h-7fh) ? 2008 microchip technology inc. ds22029d-page 3 34aa02/34lc02 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ..........................................................................................................-0.3v to v cc +1.0v storage temperature ............................................................................................................ ................... -65c to +150c ambient temperature with power appl ied.............. .............. .............. .............. ........... ........... ........... ....... -40c to +125c esd protection on all pins ............................................................... ............................................................... ........................ 4kv ? notice: stresses above those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. these are stress ratings only and functional operat ion of the device at these or any other conditions above those indicated in the operation sections of the specifications is not impli ed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 1-1: dc specifications dc characteristics v cc = +1.7v to +5.5v industrial (i): t a = -40c to +85c automotive (e):t a = -40c to +125c param. no. symbol characteristic min. typ. max. units conditions ? a0, a1, a2, scl, sda and wp pins ????? d1 v ih high-level input voltage 0.7 v cc ??v? d2 v il low-level input voltage ? ? 0.3 v cc v 0.2 v cc for v cc < 2.5v d3 v hys hysteresis of schmitt trigger inputs 0.05 v cc ??v (note) d4 v ol low-level output voltage ? ? 0.40 v i ol = 3.0 ma, v cc = 2.5v d5 v hv high-voltage detect 7 ? 10 v a0 pin only, v cc < 2.2v v cc + 4.8 ? 10 v a0 pin only, v cc 2.2v 10 ? v cc + 4.8 v a0 pin only, v cc > 5.2v d6 i li input leakage current ? ? 1 av in = v ss or v cc d7 i lo output leakage current ? ? 1 av out = v ss or v cc d8 c in , c out pin capacitance (all inputs/outputs) ? ? 10 pf v cc = 5.5v (note) t a = 25c, f clk = 1 mhz d9 i cc write operating current ? 0.1 3 ma v cc = 5.5v, scl = 1 mhz d10 i cc read ? 0.05 1 ma ? d11 i ccs standby current ? ? 0.01 ? 1 5 a a industrial automotive sda = scl = v cc a0, a1, a2, wp = v ss note: this parameter is periodically sampled and not 100% tested. 34aa02/34lc02 ds22029d-page 4 ? 2008 microchip technology inc. table 1-2: ac specifications ac characteristics v cc = +1.7v to +5.5v industrial (i): t a = -40c to +85c automotive (e):t a = -40c to +125c param. no. symbol characteristic min. max. units conditions 1f clk clock frequency ? ? ? 100 400 1000 khz 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 2t high clock high time 4000 600 500 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 3t low clock low time 4700 1300 500 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 4t r sda and scl rise time (note 1) ? ? ? 1000 300 300 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 5t f sda and scl fall time (note 1) ? ? ? 1000 300 300 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 6t hd : sta start condition hold time 4000 600 250 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 7t su : sta start condition setup time 4700 600 250 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 8t hd : dat data input hold time 0 ? ns (note 2) 9t su : dat data input setup time 250 100 100 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 10 t su : sto stop condition setup time 4000 600 250 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 11 t su : wp wp setup time 4000 600 600 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 12 t hd : wp wp hold time 4700 600 600 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 13 t aa output valid from clock (note 2) ? ? ? 3500 900 400 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 14 t buf bus free time: time the bus must be free before a new transmission can start 1300 4700 ? ? ? ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (34lc02) 16 t sp input filter spike suppression (sda and scl pins) ? 50 ns all except 34lc02 (note 1 and note 3) 17 t wc write cycle time (byte or page) ? 5 ms ? 18 ? endurance 1m ? cycles 25c, v cc = 5.5v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppres- sion. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchip?s web site at www.microchip.com. ? 2008 microchip technology inc. ds22029d-page 5 34aa02/34lc02 figure 1-1: bus timing data (unprotected) (protected) scl sda in sda out wp 5 7 6 16 3 2 89 13 d4 4 10 11 12 14 34aa02/34lc02 ds22029d-page 6 ? 2008 microchip technology inc. 2.0 functional description the 34xx02 has two software write-protect features that allow you to protect half of the array from being written (addresses 00h-7fh). one command, software write-protect (swp) will prevent writes to half of the array and is resettable by using the clear software write-protect (cswp) command. the other command is permanent software writ e-protect (pswp), which is not resettable and will permanently lock half the array from being written to. the device still has an external pin (wp) that allows you to protect the entire array if so desired. the 34xx02 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data, as a receiver. the bus has to be controlled by a master device, which generates the serial clock (scl), controls the bus access and gener- ates the start and stop conditions, while the 34xx02 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is determined by the master device and is, theoretically, unlimited; although only the last sixteen will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first-in, first-out (fifo) fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. exceptions to this rule relating to software write protection are described in section 7.0 ?write protec- tion? . the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end-of- data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (34xx02) will leave the data line high to enable the master to generate the stop condition. note: the 34xx02 does not generate any acknowledge bits if an internal programming cycle is in progress. ? 2008 microchip technology inc. ds22029d-page 7 34aa02/34lc02 figure 3-1: data transfer sequence on the serial bus 3.6 device addressing a control byte is the first byte received following the start condition from the master device. the first part of the control byte consists of a 4-bit control code which is set to ? 1010 ? for normal read and write operations and ? 0110 ? for writing to the write-protect register. the control byte is followed by three chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 34xx02 devices on the same bus and are used to determine which device is accessed. the chip select bits in the control byte must correspond to the logic lev- els on the corresponding a2, a1 and a0 pins for the device to respond. the eighth bit of slave address determines if the master device wants to read or write to the 34xx02 (figure 3-2). when set to a one, a read operation is selected. when set to a zero, a write operation is selected. figure 3-2: control byte allocation 4.0 write operations 4.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits) and the r/w bit, which is a logic low, are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow, once it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 34xx02. after receiving another acknowledge signal from the 34xx02, the master device will transmit the data word to be written into the addressed memory location. the 34xx02 acknowledges again and the master generates a stop condition. this init iates the internal write cycle, which means that during this time, the 34xx02 will not generate acknowledge signals (figure 4-1). if an attempt is made to write to the array when the software or hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. the write cycle time must be observed even if the write protection is enabled. 4.2 page write the write control byte, word address and the first data byte are transmitted to the 34xx02 in the same way as in a byte write. instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 34xx02, which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. upon receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition operation control code chip select r/w read 1010 a2 a1 a0 1 write 1010 a2 a1 a0 0 write-protect register 0110 a2 a1 a0 0 or start read/write slave address r/w a 1 0 1 0 a2 a1 a0 0 1 1 0 a2 a1 a0 34aa02/34lc02 ds22029d-page 8 ? 2008 microchip technology inc. internal write cycle will begin (figure 4-2). if an attempt is made to write to the a rray when the hardware write protection has been enabled, the device will acknowl- edge the command, but no data will be written. the write cycle time must be ob served even if the write protection is enabled. figure 4-1: byte write figure 4-2: page write note: page write operations are limited to writing bytes within a single physical page, regard- less of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size ? 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore neces- sary for the application software to prevent page write operations that would attempt to cross a page boundary. s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k s p bus activity master sda line bus activity s t a r t control byte word address (n) data (n) data (n + 15) s t o p a c k a c k a c k a c k a c k data (n + 1) ? 2008 microchip technology inc. ds22029d-page 9 34aa02/34lc02 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally ti med write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes 34aa02/34lc02 ds22029d-page 10 ? 2008 microchip technology inc. 6.0 read operation read operations are initiated in the same way as write operations, with the exce ption that the r/w bit of the slave address is set to ? 1 ?. there are three basic types of read operations: current address read, random read and sequential read. 6.1 current address read the 34xx02 contains an address counter that maintains the address of the last word accessed, inter- nally incremented by ? 1 ?. therefore, if the previous access (either a read or write operation) was to address n , the next current address read operation would access data from address n+1 . upon receipt of the slave address with r/w bit set to ? 1 ?, the 34xx02 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 34xx02 discontinues transmission (figure 6-1). 6.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the 34xx02 as part of a write operation. once the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a ? 1 ?. the 34xx02 then issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 34xx02 discontinues transmission (figure 6-2). 6.3 sequential read sequential reads are initiated in the same way as a random read, with the exce ption that after the 34xx02 transmits the first data byte , the master issues acknowl- edge, as opposed to a stop condition in a random read. this directs the 34xx02 to transmit the next sequen- tially addressed 8-bit word (figure 6-3). to provide sequential reads, the 34xx02 contains an internal address pointer, which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 6.4 contiguous addressing across multiple devices the chip select bits (a2, a1, a0) can be used to expand the contiguous address space for up to 16k bits by adding up to eight 34xx02 devices on the same bus. in this case, software can use a0 of the control byte as address bit a8; a1 as address bit a9, and a2 as address bit a10. it is not possible to sequentially read across device boundaries. 6.5 noise protection and brown-out the 34xx02 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.35v at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. figure 6-1: current address read sp bus activity master sda line bus activity s t o p control byte data (n) a c k n o a c k s t a r t ? 2008 microchip technology inc. ds22029d-page 11 34aa02/34lc02 figure 6-2: random read figure 6-3: sequential read s p s bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k p bus activity master sda line bus activity s t o p control byte a c k n o a c k data (n) data (n + 1) data (n + 2) data (n + x) a c k a c k a c k 34aa02/34lc02 ds22029d-page 12 ? 2008 microchip technology inc. 7.0 write protection the 34xx02 has two software write-protect features (swp and pswp) that allows the lower half of the array (addresses 00h-7fh) to be wr ite-protected, as well as a wp pin that can be used to protect the entire array. the permanent software write-protect feature is enabled by sending the device a special command. once this feature has been enabled, it cannot be reversed. the resettable software write-protect feature is also enabled by sending the device a special command but can be reset by issuing another special command. in addition to the software protect features, there is a wp pin that can be used to write-protect the entire array, regardless of whether the software write- protect register has been written or not. table 7-2 and table 7-3 describe how the 34xx02 will acknowledge specific commands under various circumstances. 7.1 hardware write protection the wp pin allows the user to write-protect the entire array (00-ff) when the pin is tied to v cc . if the pin is tied to v ss the write protection is disabled. 7.2 software write protection (swp) and clear software write protection (cswp) in addition to hardware write-protect the 34xx02 has an additional software write-protect feature that, when set, protects the first 128 bytes (00-7fh) of the array from being written. setting the software write protection is done by sending the swp instruction. swp can also then be cleared by issuing a cswp instruction (see figure 7-1). these two instructions follow the same format as the byte write instruction with the exception of the device type identifier, (typically ? 1010 ?, instead changes to ? 0110 ?). once this identifier is recognized by the device, the rest of the byte write command, address and data, are ?don?t cares?. in addition to the identifier, high voltage must be applied to the a0 pin of the device and specific levels must be present on a1 and a2. see table 7-1 for the available commands. 7.3 permanent software write-protect (pswp) the permanent software write protection, or pswp is another instruction that may be used to permanently protect the first 128 byte of the array. once this command is issued, the user will no longer have the ability to clear this feature regardless of instruction, power cycling, or state of the wp pin. also, once this instruction has been exec uted, the device will no longer acknowledge the device identifier ? 0110 ?. figure 7-1: software write protecti on for swp, cswp, pswp, or cpswp bus activity master sda line bus activity s t a r t control byte address byte data s t o p a c k a c k a c k s 0110 0 a 2 a 1 a 0 p ?don?t care? ?don?t care? ? 2008 microchip technology inc. ds22029d-page 13 34aa02/34lc02 table 7-2: acknowledge table for writ e or write protection with r/w = 0 table 7-3: acknowledge table for writ e or write protection with r/w = 1 table 7-1: software write protection instruction set wp = 0 address pins device type iden tifier chip select bits r/w a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 swp v ss v ss v hv 0110 0 0 1 0 cswp v ss v cc v hv 0110 0 1 1 0 pswp a2 a1 a0 0110 a2 a1 a0 0 read swp v ss v ss v hv 0110 0 0 1 1 read cswp v ss v cc v hv 0110 0 1 1 1 read pswp a2 a1 a0 0110 a2 a1 a0 1 1. a0 is used to detect v hv for the swp and cswp commands. 2. b3, b2 and b1 are compared to the a2, a1 and a0 external pins, respectively on the 34xx02. status write- protect instruction ack address ack data byte ack write cycle permanently protected x pswp , swp , cswp no ack don?t care no ack don?t care no ack no page or byte write in lower 128 bytes ack address ack data no ack no protected with swp 0 swp no ack don?t care no ack don?t care no ack no cswp ack don?t care ack don?t care ack yes pswp ack don?t care ack don?t care ack yes page or byte write in lower 128 bytes ack address ack data no ack no 1 swp no ack don?t care no ack don?t care no ack no cswp ack don?t care ack don?t care no ack no pswp ack don?t care ack don?t care no ack no page or byte write ack address ack data no ack no not protected 0 pswp , swp , or cswp ack don?t care ack don?t care ack yes page or byte write ack address ack data ack yes 1 pswp , swp , or cswp ack don?t care ack don?t care no ack no page or byte write ack address ack address no ack no status instruction ack permanently protected pswp , swp , cswp no ack protected with swp swp no ack cswp ack pswp ack not protected pswp , swp , cswp ack 34aa02/34lc02 ds22029d-page 14 ? 2008 microchip technology inc. 8.0 pin descriptions the descriptions of the pins are listed in table 8-1. table 8-1: pin function table 8.1 a0, a1, a2 the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight 34xx02 devices may be connected to the same bus by using different chip select bit combinations. these inputs must be connected to either v ss or v cc . the a0 pin is also used to detect v hv . 8.2 serial address/data input/output (sda) this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal. therefore, the sda bus requires a pull- up resistor to v cc (typical 10 k for 100 khz, 2 k for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 8.3 serial clock (scl) this input is used to synchronize the data transfer to and from the device. 8.4 write-protect (wp) this is the hardware write-protect pin. it can be tied to v cc or v ss . if tied to v cc , the hardware write protection is enabled. if the wp pin is tied to v ss , the hardware write protection is disabled. symbol pdip soic tssop msop tdfn sot-23 description a0 1 1 1 1 1 5 chip address input a1 2 2 2 2 2 4 chip address input a2 3 3 3 3 3 nc chip address input v ss 4 4 4 4 4 2 ground sda 5 5 5 5 5 3 serial address/data i/o scl 6 6 6 6 6 1 serial clock wp 7 7 7 7 7 nc write-protect input v cc 8 8 8 8 8 6 +1.7v to 5.5v power supply ? 2008 microchip technology inc. ds22029d-page 15 34aa02/34lc02 9.0 packaging information 9.1 package marking information xxxxxxxx txxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (3.90 mm) example: xxxxxxxt xxxxyyww nnn 34aa02 i/p 3ec 0810 34lc02i sn 0810 3ec 8-lead msop example: xxxxxt ywwnnn 34aa2i 8103ec 8-lead tssop example: xxxx tyww nnn 34v2 i810 3ec 8-lead 2x3 tdfn xxx yww nn example: 3 e 3 e aj2 810 3e part number 1st line marking codes tssop msop tdfn 34aa02 34a2 34aa2t 2j2 34lc02 34l2 34vl2t 2j5 34aa02/34lc02 ds22029d-page 16 ? 2008 microchip technology inc. example: 6-lead sot-23 xxnn skec sot-23 marking codes device 34aa02 34lc02 i-temp stnn sknn e-temp svnn slnn pb-free topside mark is same; pb-free noted only on carton label. legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custome r-specific information. 3 e 3 e note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. * standard otp marking consists of microchip part num ber, year code, week code, and traceability code. ? 2008 microchip technology inc. ds22029d-page 17 34aa02/34lc02 !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# / !# '! #& .0 1,21 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 7,8. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - - ## 4 >#& . < : 9& -< -? & & 9 - 9 # 4!! < 6 9 #>#& ) ? 9 * 9 #>#& ) < : * + 1 = = - n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c * , <1 34aa02/34lc02 ds22029d-page 18 ? 2008 microchip technology inc. ! ""#$%& !' !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & = = ## 4 4!! = = & # %% + = : >#& . ?1, ## 4 >#& . -1, : 9& 1, , '% @ & a = 3 &9& 9 = 3 & & 9 .3 3 & b = #& ) - = # %& b = b # %&1 && ' b = b d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h * , 1 ? 2008 microchip technology inc. ds22029d-page 19 34aa02/34lc02 ! ""#$%& !' 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 34aa02/34lc02 ds22029d-page 20 ? 2008 microchip technology inc. () )" * ! (+%+ ( ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . ?1, ## 4 >#& . - ## 4 9& - - 3 &9& 9 ? 3 & & 9 .3 3 & b = #& ) = - d n e e1 note 1 12 b e c a a1 a2 l1 l * , ? 2008 microchip technology inc. ds22029d-page 21 34aa02/34lc02 , " ! *-, , ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . 1, ## 4 >#& . -1, : 9& -1, 3 &9& 9 ? < 3 & & 9 .3 3 & b = #& ) = d n e e1 note 1 1 2 e b a a1 a2 c l1 l * , 1 34aa02/34lc02 ds22029d-page 22 ? 2008 microchip technology inc. . $ *-, /00%12 (. 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2008 microchip technology inc. ds22029d-page 23 34aa02/34lc02 . $ *-, /00%12 (. 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 34aa02/34lc02 ds22029d-page 24 ? 2008 microchip technology inc. 3 ! (" "!( !(/ '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 ? & 1, :"&!#9 # & 1, : 8 & = ## 4 4!! < = - & # %% = : >#& . = - ## 4 >#& . - = < : 9& = - 3 &9& 9 = ? 3 & & 9 - = < 3 & b = -b 9 # 4!! < = ? 9 #>#& ) = b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1 * ,<1 ? 2008 microchip technology inc. ds22029d-page 25 34aa02/34lc02 appendix a: revision history revision a (1/2007) original release of this document. revision b (2/2007) replaced package drawings. revision c (2/2008) added tdfn and sot-23 package info; removed ?vl? part. revision d (4/2008) updated product identification system table, example (e). 34aa02/34lc02 ds22029d-page 26 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds22029d-page 27 34aa02/34lc02 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://suppo rt.microchip.com 34aa02/34lc02 ds22029d-page 28 ? 2008 microchip technology inc. reader response it is our intention to provide you wit h the best documentation possible to ensur e successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to t he technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds22029d 34aa02/34lc02 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2008 microchip technology inc. ds22029d-page29 34aa02/34lc02 product identification system to order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office. part no. x /xx package temperature range device device: 34aa02: = 1.7v, 2 kbit i 2 c serial eeprom 34aa02t: = 1.7v, 2 kbit i 2 c serial eeprom (tape and reel) 34lc02: = 2.2v, 2 kbit i 2 c serial eeprom 34lc02t: = 2.2v, 2 kbit i 2 c serial eeprom (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: ot = plastic small outline (sot-23), 6-lead p = plastic dip (300 mil body), 8-lead sn = plastic soic (3.90 mm body), 8-lead st = plastic tssop (4.4 mm), 8-lead ms = plastic micro small outline (msop), 8-lead mny* = plastic dual flat, no lead package (2x3 mm body), 8-lead examples: a) 34aa02-i/p: industrial temperature, 1.7v, pdip package b) 34aa02-i/sn: industrial temperature, 1.7v, soic package c) 34aa02t-e/ms: tape and reel, automotive temperature, 1.7v, msop package d) 34lc02-i/p: industrial temperature, 2.2v, pdip package e) 34lc02-i/mny: industrial temperature, 2.2v, dfn package f) 34lc02t-e/ms: tape and reel, automotive temperature, 2.2v, msop package note 1: ?y? indicates a nickel palladi um gold (nipdau) finish. 34aa02/34lc02 ds22029d-page 30 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds22029d-page 31 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds22029d-page 32 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 |
Price & Availability of 34LC02T-EOT
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